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1 features programmable gain, network balance and impedance transformerless 2-4wire conversion constant current with constant voltage fallback for long loop capability pin compatible with mh88632 and mh88628. unbalance detection (tip, ring ground sensing) auto ring trip on-hook transmission (ani) capability compatible with requirements of ccitt, doc/ fcc and csa/uls excellent power dissipation (sil vertical mounting) 12/16khz meter pulse injection control solid state tip/ring reversals applications on/off premise pbx line cards did (direct inward dial) line cards central of?e line cards description the zarlink MH88625 slic provides all of the functions required to interface 2-wire off premise subscriber loops to a serial tdm, pcm, switching network of a modern pbx. the MH88625 is manufactured using thick-?m hybrid technology which offers high voltage capability, reliability and high density resulting in signi?ant printed circuit board area savings. a complete line card can be implemented with very few external components. figure 1 - functional block diagram shk ns n2 natt rrd revc z900 z600 z1 z2 grx1 grx0 rx gtx1 gtx0 tx ud tf2 tf1 tip rf2 rf1 ring n1 lca vdd rngc rgnd vrly vee agnd matched feed resistors unbalance detection ring relay driver driver circuitry and speech circuit tip/ring external signal input loop current set switch-hook threshold switch-hook detect impedance network ring filter 2-4 wire conversion gain adjust vba t lgnd reversal esi ese ordering information MH88625 40 pin sil package 0 c to 70 c MH88625 did/ops slic ds5167 issue 7 august 1999 preliminary information
MH88625 preliminary information 2 figure 2 - pin connections pin description pin # name description 1 tip tip lead. connects to the ?ip lead of subscriber line. 2 ring ring lead . connects to the "ring" lead of the subscriber line. 3 tf1 tip feed 1. access point for balanced ringing. normally connects to tf2. 4 tf2 tip feed 2. access point for balanced ringing. normally connects to tf1. 5 rf1 ring feed 1. access point for balanced ringing. normally connects to rf2. 6 rf2 ring feed 2. access point for balanced ringing. normally connects to rf1. 7 lgnd battery ground . v bat return path. connected to system s energy dumping ground. 8 lca current limit set (input). the current limit is set by connecting an external resistor to ground. for 30ma default current, this pin is tied to gnd 9 vbat battery voltage . typically -48vdc is applied to this pin. 10 ic internal connection . this pin is internally connected and must be left open. 11 rgnd relay driver ground connection. 12 vrly relay supply voltage connection . 13 rrd ring relay drive (output). connects to ring relay coil. 14 rngc ring relay control (input). a logic low enables the ring relay drive (rrd ) output which activates the ring relay. the internal auto ring trip circuitry de-activates the relay drive output upon detection of switch-hook. 15 revc reversal control (input). a logic high reverse the internal tip and ring connections. 16 esi external signal input. 12/16khz meter pulse input. 17 ese external signal enable. 12/16khz meter pulse enable. 18 agnd analog ground. v dd and v ee return path. 19 natt network balance at+t node. connects to n1 for a network balance impedance of at&t compromise (350 ? + 1k ? // 210nf); the device s input impedance must be set to 600 ? . this node is active only when ns is at logic high. this node should be left open circuit when not used. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 n2 z900 z1 z2 tx rx gtxo gtx1 grxo grx1 ic z600 ns shk ud ic ic ic vee vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 tip ring tf1 tf2 rf1 rf2 lgnd lca vbat ic rgnd vrly rrd rngc revc esi ese agnd natt n1
preliminary information MH88625 3 20 n1 network balance node 1 (input). 0.1 times the impedance between pins n1 and n2 must match the device s input impedance, while 0.1 times the impedance between pins n1 and agnd is the device s network balance impedance. this node is active only when ns is at logic high. this node may be terminated when not used (i.e., ns at logic low). 21 n2 network balance node 2 (output). see n1 for description. 22 z900 line impedance 900 ? node. connects to z1 for a line impedance of 900 ? . this node should be left open circuit when not used. 23 z1 line impedance node 1 (input) . 0.1 times the times the impedance between pins z1 and z2 is the device s line impedance. this node must always be connected. 24 z2 line impedance node 2 (output). 0.1 times the times the impedance between pins z1 and z2 is the device s line impedance. this node should be left open circuit when not used. 25 tx transmit (output) . 4-wire (agnd) referenced audio output. 26 rx receive (input) . 4-wire (agnd) referenced audio input. 27 gtxo transmit gain node 0 . connects to gtx1 for 0db transmit gain. 28 gtx1 transmit gain node 1 . connects to a resistor to agnd for transmit gain adjustment. 29 grxo receive gain node 0. connects to grx1 for 0db gain. 30 grx1 receive gain node 1. connects to a resistor to agnd to receive gain adjustment. 31 ic internal connection. this pin is internally connected and must be left open. 32 z600 line impedance 600 ? node (output). connects to z1 for a line impedance of 600 ? . this pin should be left open circuit when not used. 33 ns network balance setting (input. the logic level at ns selects the network balance impedance. a logic 0 enables an internal balance equivalent to the input impedance (zin). while a logic 1 enables an external balance 0.1 times the impedance between pins n1 and agnd balanced to 0.1 times the impedance between pins n1 and n2. the impedance between n1 and n2 must be equivalent to 10 times the input impedance (zin). 34 shk off-hook indication (output). a logic low output indicates when the subscriber equipment has gone off-hook. 35 ud unbalance detect (output). a log ic low output indicates when the dc current ?w in the tip and ring leads is unbalanced, indicating that the subscriber equipment has grounded the ring lead. 36,37 38 ic internal connection. these pins are internally connected and must be left open 39 v ee negative supply voltage. -5v dc. 40 v dd positive supply voltage. +5v dc. pin description (continued) pin # name description
MH88625 preliminary information 4 functional description the slic uses a transformerless electronic 2-wire to 4-wire conversion which can be connected to a codec to interface the 2 wire subscriber loops to a time division multiplexed (tdm) pulse code modulated (pcm) digital switching network. for analog applications, the tx and rx of the 2-4 wire converter can be connected directly to an analog crosspoint switch such as the mt8816. powering of the line is provided through precision battery feed resistors. the MH88625 also contains control, signalling and status circuitry which combines to provide a complete functional solution which simpli?s the manufacture of line cards. this circuitry is illustrated in the functional block diagram in figure 1. the MH88625 is designed to be pin compatible with zarlink s mh88632 and mh88628. this allows a common pcb design with common gain, input impedance and network balance. approvals fcc part 68, ccitt, doc cs-03, ul 1950, iec950, can/csa 22.2 no.225-m90 and ansi/eia/tia-464- a are system level safety standards and performance requirements. as a component of a system, the MH88625 is designed to comply with the applicable requirements of these speci?ations battery feed the loop current for the subscriber equipment is sourced through a pair of matched 200 ? resistors connected to the tip and ring. the two wire loop is biased such that the ring lead is 2v above vbat (typically -46v) and the tip lead is 2v below lpgd (typically -2v) during constant voltage, constant current mode. the slic is designed for a nominal battery voltage of -48vdc and can provide the maximum loop current of 45ma under the condition. the MH88625 is designed to operate down to a minimum of 16ma dc, with a battery voltage of -44v. the tip and ring output drivers can operate within 2v of vbat and lgnd rails. this permits a maximum loop range of 2300 ? loop current setting the MH88625 slic provides a constant current with constant voltage fallback. this design feature provides for long loop capability regardless of the constant current setting. refer to graph 1. the lca (loop current adjust) pin is an input to an internal resistor divider network which generates a bias voltage. the loop current is proportional to this voltage. the loop current can be set between 20 and 45ma by various connections to the lca pin as illustrated in graph 2 and figure 8. the loop current during a fault condition will be limited to a safe level. primary over-current protection is inherent in the current limiting feature of the 200 ? battery feed resistors. refer to graph 1. receive and transmit audio path the audio signal of the 2-wire side is sensed differentially across the external 200 ? feed resistors and is passed on to a second differential ampli?r stage in the 2w/4w conversion block. this block sets the transmit gain on the 4-wire side and cancels signals originating from the receive input before outputting the signal. programmable transmit and receive gain transmit gain (tip-ring to tx) and receive gain (rx to tip-ring) are programmed by connecting external resistors (rrx and rrt) from grxi to agnd and from gtx1 to agnd as indicated in figure 3 and tables 1 and 2. the programmable gain range is from -12db to +6db; this wide range will accommodate almost any loss plan. alternatively, the default receive gain of 0db and transmit gain of 0db can be obtained by connecting grx0 to grx1 and gtx0 to gtx1. in addition, a receive gain of +6db and transmit gain of +6db can be obtained by not connecting resistors rrx and rtx. for correct gain programming, the MH88625 |